Syllabus - Computer Architecture (SD301)

Computer Science and Design

Computer Architecture (SD301)

III-Semester

Unit I

Review of Digital Logic Circuits, Digital Logic Components and Data representation.Computer Arithmetic: Integer and Floating Point Arithmetic operations.

Computer Organization v/s Architecture,Milestonesin Computer Architecture, Basic Structure of Computer System, Components of Computer System- CPU; Memory; System Bus- Bus width, Bus Operations; I/O subsystem. CPU Organization: General Register Organization- Memory Register, Instruction Register; Control Word, Stack Organization; ALU, Control Unit.

Unit II

(A) Machine Language Level/Instruction Set Architecture (ISA) level: Instruction Set- Machine Instruction Characteristics, Types of operands, Types of operations; Instruction Types, Instruction Formats, Addressing Modes; Registers, Program Counter; Instruction Execution Cycle: Fetch and Execution cycle; Interrupts and Traps, Sources of interrupts, Interrupt identification and priorities, Interrupt servicing. Case Study of 8086 Microprocessor.

(B) Control Unit: Hardwired Control Unit; Micro-programmed Control Unit- Micro Instructions, Micro Instruction Formats, Micro Instruction Control, Micro program sequencer, Execution of Micro Instructions.

Unit III

Memory Organization: Memory Hierarchy, Main memory-RAM, ROM; Memory Technologies; Memory Addresses, Memory Address Map; Flash Memory; Associative Memory, Cache Memory: Cache Structure and Design, Mapping Schemes, Replacement Algorithms, Improving Cache Performance; Concept of L1, L2, L3 Cache. Secondary Memory –Magnetic Tape, Magnetic Disk, Optical Disks, Solid State Disk.

Unit IV

I/O Organization: Data Transfer- Serial, Parallel, Synchronous, Asynchronous Modes of Data Transfer, I/O Techniques- Programmed I/O, Interrupt driven I/O, Direct Memory Access (DMA); External Interconnection Standards (I/O Interfaces): PCI Bus, PCI Express, SCSI Bus, USB; I/O Channels and I/O Processors; I/O Instructions.

Unit V

level Parallel Architectures: On-chip parallelism, Thread parallelism; Multicore Processor Architecture; Processor level parallelism; Overview of Pipelining, Vector Processing and Array Processing. RISC vs CISC Architectures. Introduction to ARM processor and its architecture. Introduction to Assembly Language Programming. Case study of architectures: Intel, AMD.

Course Objective

The main objective of this course is to give understanding about various architectures of Computers and their components, functioning of the computer system; to introduce various parallel architectures and recent trends in computer architectures.

Course Outcome

["Illustrate architecture of a computer, its components and their interconnection.", "Describe execution of instruction in a computer.", "Identify the addressing modes used in macro instruction.", "Design programs in assembly language.", "Understand the importance of parallel architecture."]

Practicals

Reference Books

  • William Stallings, “Computer Organization and architecture”, Pearson.

  • Tannenbaum and Austin, “Structured Computer Organization”, PHI.

  • Michael J. Flynn “Computer Architecture: Pipelined and Parallel Processor Design

  • V. Carl Hamacher, “Computer Organization”, McGraw Hill.

  • John P. Hayes, “Computer Architecture and Organization”, TMH

  • Morris Mano, “Computer System Architecture”, PHI.

  • David A. Patterson and John L. Hennessy, “Computer Organization and Design: The Hardware/Software Interface”, Fourth Edition, Morgan Kauffman