Explain the formation of depletion layer with external bias.

Formation of Depletion Layer in a PN Junction Diode

The depletion layer in a PN junction diode is a region around the junction where mobile charge carriers (electrons and holes) are absent. This region is formed when a diode is created by doping one side of a semiconductor material with acceptors (to create a P-type region) and the other side with donors (to create an N-type region). Here's a step-by-step explanation of how the depletion layer is formed:

Step 1: Doping the Semiconductor

P-type Material	N-type Material
Contains acceptor impurities (e.g., Boron)	Contains donor impurities (e.g., Phosphorus)
Has an abundance of holes (positive charge carriers)	Has an abundance of electrons (negative charge carriers)

Step 2: Formation of PN Junction

When the P-type and N-type materials are brought into contact, a PN junction is formed.

Step 3: Diffusion of Charge Carriers

Due to the concentration gradient, electrons from the N-type region diffuse into the P-type region, and holes from the P-type region diffuse into the N-type region.

Step 4: Formation of Depletion Region

As electrons and holes diffuse, they recombine near the junction. This leaves behind immobile ions: negatively charged acceptor ions in the P-type region and positively charged donor ions in the N-type region. This area devoid of mobile charge carriers is the depletion region.

Step 5: Establishment of Electric Field

The immobile ions create an electric field ( E ) that opposes further diffusion of charge carriers. The potential difference across the depletion region is called the built-in potential ( V_{bi} ).

Step 6: Equilibrium

Eventually, an equilibrium is reached where the electric field prevents further diffusion of charge carriers. The width of the depletion region depends on the doping levels and the built-in potential.

Applying External Bias

An external bias (voltage) applied across the PN junction affects the width of the depletion layer.

Forward Bias

When a positive voltage is applied to the P-type material and a negative voltage to the N-type material, the external electric field reduces the built-in potential barrier.

Without Bias	With Forward Bias
Depletion layer is at equilibrium width	Depletion layer narrows
Electric field opposes carrier diffusion	Electric field is reduced, allowing carrier diffusion
No current flows (except for a small leakage current)	Current flows as carriers are injected across the junction

Reverse Bias

When a negative voltage is applied to the P-type material and a positive voltage to the N-type material, the external electric field increases the built-in potential barrier.

Without Bias	With Reverse Bias
Depletion layer is at equilibrium width	Depletion layer widens
Electric field opposes carrier diffusion	Electric field is increased, further preventing carrier diffusion
No current flows (except for a small leakage current)	Very little current flows (reverse saturation current) due to the widened depletion region

Formulas

The potential barrier can be described by the built-in potential ( V_{bi} ), which is given by:

[ V_{bi} = \frac{kT}{q} \ln \left( \frac{N_A N_D}{n_i^2} \right) ]

where:

• ( k ) is the Boltzmann constant,
• ( T ) is the temperature in Kelvin,
• ( q ) is the charge of an electron,
• ( N_A ) is the acceptor doping concentration,
• ( N_D ) is the donor doping concentration,
• ( n_i ) is the intrinsic carrier concentration.

The width of the depletion region ( W ) can be calculated using:

[ W = \sqrt{\frac{2 \epsilon (V_{bi} - V)}{q} \left( \frac{1}{N_A} + \frac{1}{N_D} \right) } ]

where:

• ( \epsilon ) is the permittivity of the semiconductor,
• ( V ) is the applied bias voltage (positive for forward bias, negative for reverse bias).

Example

Consider a silicon PN junction at room temperature with ( N_A = 10^{16} ) cm(^{-3}) and ( N_D = 10^{17} ) cm(^{-3}). The intrinsic carrier concentration ( n_i ) for silicon at room temperature is approximately ( 1.5 \times 10^{10} ) cm(^{-3}). Let's calculate the built-in potential ( V_{bi} ) without any external bias.

Using the formula for ( V_{bi} ):

[ V_{bi} = \frac{kT}{q} \ln \left( \frac{N_A N_D}{n_i^2} \right) ]

Assuming room temperature (( T = 300 ) K), and using ( k = 1.38 \times 10^{-23} ) J/K and ( q = 1.6 \times 10^{-19} ) C, we get:

[ V_{bi} = \frac{(1.38 \times 10^{-23} \text{ J/K}) (300 \text{ K})}{(1.6 \times 10^{-19} \text{ C})} \ln \left( \frac{(10^{16} \text{ cm}^{-3})(10^{17} \text{ cm}^{-3})}{(1.5 \times 10^{10} \text{ cm}^{-3})^2} \right) ]

[ V_{bi} \approx 0.0259 \times \ln \left( \frac{10^{33}}{2.25 \times 10^{20}} \right) ]

[ V_{bi} \approx 0.0259 \times \ln \left( 4.44 \times 10^{12} \right) ]

[ V_{bi} \approx 0.0259 \times 28.16 ]

[ V_{bi} \approx 0.73 \text{ V} ]

This is the built-in potential without any external bias. Applying an external bias would modify this potential and consequently the width of the depletion layer.